IC Substrate Coefficient of Thermal Expansion (CTE) Temperature Testing: Methods, Standards, and Rel

IC substrate coefficient of thermal expansion (CTE) temperature testing measures how package substrate materials deform dimensionally as temperature rises, using techniques such as thermomechanical analysis (TMA) to quantify in-plane and z-axis expansion behavior. Accurate CTE characterization is essential for matching the substrate to the silicon die and the motherboard, minimizing warpage, and preventing solder joint fatigue, delamination, and via cracking in flip-chip, BGA, and memory packages. This article explains the technical principles, sample types, test items, measurement methods, standards, and practical applications of CTE temperature testing for IC substrates.

Technical Overview

The coefficient of thermal expansion (CTE) describes the fractional dimensional change of a material per degree of temperature change, typically expressed in ppm/°C. In integrated circuit packaging, the IC substrate (also called the package substrate or interposer) sits between a silicon die with a CTE of approximately 2.6 ppm/°C and a printed circuit board with a CTE of roughly 14–17 ppm/°C. Because the substrate experiences steep thermal gradients and thermal cycling during reflow soldering, power cycling, and field operation, any mismatch in expansion between these layers generates thermomechanical stress at every interface.

CTE temperature testing therefore evaluates the substrate material across a defined temperature range, usually from room temperature to 250–300°C, to determine how expansion behaves below and above the glass transition temperature (Tg). The results directly influence substrate design rules, material selection, warpage simulation, and long-term reliability prediction.

IC substrates exhibit strongly anisotropic expansion behavior, which is why testing must distinguish between the two principal directions:

• X/Y in-plane CTE: governed by glass fiber or filler reinforcement in the core; critical for die attach, bump joint stress, and coplanarity with silicon.
• Z-axis out-of-plane CTE: dominated by resin behavior; critical for plated via reliability, because excessive z-expansion stresses hole walls and interconnects during reflow.

Typical values for common substrate materials include BT (bismaleimide triazine) cores at approximately 10–15 ppm/°C in-plane, low-CTE silica-filled cores at 6–10 ppm/°C, and build-up dielectric films such as Ajinomoto Build-up Film (ABF) exhibiting z-axis expansion of roughly 25–45 ppm/°C below Tg and well above 100 ppm/°C beyond Tg. Exceeding these windows during temperature testing signals elevated risk of warpage, solder ball detachment, and interconnect failure.

Testing Samples

Copper-Clad Laminate Core Materials

Raw BT or epoxy copper-clad laminate (CCL) sheets intended for substrate cores are sampled with the copper fully etched away so that resin and reinforcement behavior can be measured independently. Panels are typically cut to squares of approximately 6.4 mm × 6.4 mm for z-axis testing, with total thickness of at least 0.5 mm to ensure probe contact stability.

Build-up Dielectric Films

Photosensitive or thermosetting build-up films, including ABF-type materials, are laminated and cured under production conditions before sampling. Because a single film layer may be only 15–40 µm thick, multiple cured layers are stacked to reach a measurable height, and the reported CTE reflects the cured film properties rather than the raw B-stage material.

Finished Multilayer IC Substrates

As-fabricated substrate coupons containing core, build-up layers, copper pattern, and solder mask can be tested to capture the composite expansion behavior of the real product stack. These samples verify that processing, curing, and copper distribution have not shifted expansion characteristics beyond the design envelope.

Solder Mask and Coating Materials

Solder resist layers contribute significantly to overall substrate warpage because they expand at higher rates than the underlying laminate. Freestanding cured specimens or coated panels are tested to characterize their individual CTE contribution.

Specimen Conditioning

All samples are edge-machined for parallelism within approximately 25 µm, pre-dried at 105–120°C for 1–2 hours to remove absorbed moisture, and conditioned at 23 ± 2°C and 50 ± 5% relative humidity before testing. A minimum of three to five specimens per material lot is recommended for statistical validity.

Testing Items

A complete CTE temperature test program for IC substrates typically reports the following parameters:

• In-plane CTE (X/Y) below Tg (alpha 1): the expansion slope measured over a defined low-temperature window, commonly 50–150°C.
• Z-axis CTE below Tg (alpha 1): the thickness-direction expansion slope below the glass transition, a primary qualification metric for core and build-up dielectrics.
• Z-axis CTE above Tg (alpha 2): the sharply increased expansion slope beyond Tg, which drives via and interconnect stress during reflow.
• Glass transition temperature (Tg): determined from the TMA expansion curve as the intersection of the alpha 1 and alpha 2 tangent lines.
• Total z-expansion percentage: cumulative thickness increase at reference temperatures such as 240°C, 260°C, or 288°C, used to assess reflow survivability.
• CTE hysteresis and thermal history effects: comparison between first and second heating runs to distinguish as-cured behavior from post-cure stabilized behavior.
• Delamination onset: identification of sudden probe displacement or slope discontinuity indicating interfacial separation during the ramp.

Testing Methods

The dominant method is thermomechanical analysis (TMA) performed to ASTM E831 and IPC-TM-650 method 2.4.24C. A flat silica expansion probe applies a light static load of typically 5–20 mN to the specimen while a furnace ramps the temperature at 3–5°C/min under nitrogen purge of 20–50 mL/min. The instrument records dimensional change as a function of temperature, and CTE is calculated as the slope of the linear regression over the specified temperature window divided by the original specimen dimension.

Key procedural steps include:

• Instrument calibration with certified reference materials such as fused silica (approximately 0.5 ppm/°C) and aluminum (approximately 23 ppm/°C) to verify displacement accuracy across the target range.
• Zero-load baseline correction using a blank run to subtract probe and platform expansion from the specimen signal.
• Temperature programming from room temperature (or −50°C for sub-ambient characterization) up to 260–300°C, staying below the onset of resin decomposition.
• Slope extraction for alpha 1 (commonly 50–150°C), tangent-intersection determination of Tg, and slope extraction for alpha 2 (Tg + 20°C to the upper limit).
• Repeat runs on multiple specimens with reporting of mean, standard deviation, and any curve anomalies such as softening shoulders or delamination events.

For in-plane CTE, several complementary techniques are used because TMA is inherently optimized for the thickness direction:

• Push-rod dilatometry per ASTM E228, using long strip specimens to improve resolution of low in-plane expansion values.
• Digital image correlation (DIC) with speckle-patterned samples imaged inside a thermal chamber, providing full-field strain mapping in x and y simultaneously.
• Foil strain gauge methods bonded to the substrate, suitable for larger coupons and thermal cycling profiles.
• Optical interferometry or shadow moiré systems for non-contact displacement measurement at elevated temperature.

Applicable specification references include IPC-TM-650 2.4.24/2.4.24C, ASTM E831, ASTM E228, ASTM D3386, and the material requirements defined in the relevant IPC-4101 or IPC-4103 slash sheets. Typical acceptance limits are material-dependent, but common qualification targets are in-plane alpha 1 below 10–17 ppm/°C, z-axis alpha 1 below 40–45 ppm/°C, z-axis alpha 2 below 200–300 ppm/°C, and total z-expansion at 260°C below approximately 3–4%.

Applications

CTE temperature test data underpin nearly every stage of IC substrate development and deployment:

• Material qualification: incoming inspection and supplier certification for BT laminates, low-CTE cores, ABF build-up films, and solder resins against datasheet limits.
• Flip-chip BGA (FCBGA) and high-density package design: selecting core materials whose in-plane CTE bridges the gap between silicon and board to control bump joint stress.
• Memory and storage substrates: verifying expansion stability for DDR, eMMC, and SSD packaging subjected to repetitive thermal cycles.
• 2.5D and 3D advanced packaging: characterizing interposers and redistribution layers where expansion mismatch directly impacts microbump and through-silicon via reliability.
• Warpage prediction: feeding measured alpha 1, alpha 2, and Tg values into finite element and laminate theory models to predict coplanarity across reflow and operation.
• Solder joint life estimation: supporting Coffin–Manson type fatigue calculations for thermal cycling qualification such as −40°C to 125°C air-to-air cycling.
• Process optimization: confirming that lamination pressure, curing schedules, and post-cure treatments produce the intended expansion properties.
• Automotive, 5G, and high-power electronics: demonstrating long-term reliability in harsh environments where wide temperature swings amplify CTE mismatch damage.

FAQ

Why is CTE mismatch so critical for IC substrates?

The substrate is mechanically sandwiched between a silicon die expanding at roughly 2.6 ppm/°C and a PCB expanding at roughly 14–17 ppm/°C. During reflow or thermal cycling, mismatched expansion creates shear stress at solder joints, tensile stress at the die attach interface, and bending stress in the core, which can cause joint fatigue, delamination, cracking, and excessive warpage.

What temperature range is used in CTE temperature testing?

Most substrate tests run from room temperature to 260–300°C at 3–5°C/min, which covers the full reflow profile and both below-Tg and above-Tg expansion regions. Sub-ambient programs starting at −50°C are added when packages must qualify for cold-start or automotive cycling conditions.

What is the difference between X/Y CTE and Z-axis CTE, and which matters more?

X/Y (in-plane) CTE governs die-to-substrate and substrate-to-board stress and warpage, while Z-axis (through-thickness) CTE governs stress on plated vias, pads, and interconnects during out-of-plane swelling at reflow. Both must be qualified; in-plane targets silicon matching, and z-axis targets via integrity.

Which standards govern the test method?

Primary references are IPC-TM-650 method 2.4.24C for TMA-based Tg and z-axis thermal expansion, ASTM E831 for linear expansion by TMA, ASTM E228 for dilatometry, ASTM D3386 for insulating materials, and IPC-4101/IPC-4103 slash sheets for material-level acceptance limits.

What are typical acceptance values for IC substrate materials?

Common qualification windows include in-plane alpha 1 of 6–17 ppm/°C, z-axis alpha 1 of 25–45 ppm/°C, z-axis alpha 2 of 100–300 ppm/°C, Tg of 150–220°C depending on resin system, and total thickness expansion at 260°C below about 3–4%. Exact limits are always set by the customer specification and package class.

How many specimens are required and how should results be reported?

At least three to five specimens per material condition should be tested after conditioning and pre-drying. Reports should include specimen geometry, copper state, conditioning history, heating rate, calculation windows, alpha 1, alpha 2, Tg, total expansion values, individual and mean results with standard deviation, and any anomalies such as delamination events.

Why do first-run and second-run CTE curves sometimes differ?

The first heating run may show additional expansion from post-cure completion, residual stress relaxation, or moisture desorption. A second run reveals the stabilized material behavior. Comparing the two runs is a useful diagnostic for incomplete cure or inadequate pre-drying, and many specifications require reporting both.

Can TMA measure in-plane CTE directly?

Standard TMA measures the thickness direction with high accuracy. In-plane CTE is better measured with macro-expansion TMA accessories on long strips, push-rod dilatometry, or non-contact optical methods such as digital image correlation and shadow moiré, which provide the resolution needed for the low expansion values typical of reinforced substrate cores.