Semiconductor Failure Analysis Experiments: Methods, Techniques, and Laboratory Testing Guide

Semiconductor failure analysis experiments are systematic laboratory investigations designed to identify the root causes of electrical, thermal, and physical failures in integrated circuits and discrete devices. By combining non-destructive inspection, electrical fault isolation, and advanced microscopy techniques, accredited third-party laboratories help manufacturers improve yield, verify reliability, and resolve field failures. This guide explains the full failure analysis workflow, common testing samples, analytical methods, applicable standards, and industrial applications.

Technical Overview

Semiconductor failure analysis (FA) is a structured investigative discipline that determines why a microelectronic device deviates from its intended electrical, mechanical, or functional behavior. A failed component rarely reveals its root cause through external symptoms alone, so modern failure analysis experiments follow a carefully sequenced protocol: confirm and characterize the failure electrically, preserve evidence through non-destructive inspection, localize the defect site, and finally expose and examine the physical anomaly at the microscopic or nanoscopic level.

Because semiconductor devices incorporate diverse materials—silicon, compound semiconductors, metals, dielectrics, polymers, and ceramics—failure analysis laboratories must integrate tools spanning electrical engineering, materials science, and surface chemistry. Typical instrumentation includes curve tracers, X-ray imaging systems, scanning acoustic microscopes, infrared thermal and photon emission cameras, focused ion beam (FIB) systems, scanning electron microscopes (SEM), transmission electron microscopes (TEM), and surface analysis spectrometers. Analytical work is commonly performed in accordance with recognized frameworks such as JEDEC guidelines, IEC standards, ASTM test methods, MIL-STD-883 test methods, AEC-Q100/Q101 qualification references, and ISO/IEC 17025 laboratory quality management requirements.

The primary objectives of a semiconductor failure analysis experiment are to confirm the failure mode, isolate the defect location with sub-micron precision, identify the physical mechanism (for example, EOS damage, electromigration, gate oxide breakdown, contamination, delamination, or solder fatigue), and provide actionable corrective recommendations for design, process, or application improvement.

Testing Samples

Integrated Circuits

Digital, analog, mixed-signal, memory, RF, and power management ICs in all package formats, including QFP, QFN, BGA, CSP, flip-chip, wafer-level packaging (WLP), and bare dies. Typical failure symptoms include functional failures, excessive leakage current, open or shorted pins, parametric drift, and intermittent behavior.

Discrete Semiconductor Devices

Diodes, Schottky devices, bipolar transistors, MOSFETs, IGBTs, thyristors, and TVS protection devices. Discrete power components frequently exhibit failures related to avalanche stress, thermal runaway, bond wire lift-off, and die-attach voiding.

Optoelectronic and Compound Semiconductor Devices

LEDs, laser diodes, photodiodes, image sensors, and GaN or SiC power devices. Analysis of these samples emphasizes epitaxial layer defects, dark line/dark spot defects, and package-induced stress effects.

Passive Components and Assemblies

Multilayer ceramic capacitors (MLCC), resistors, inductors, crystal units, and assembled printed circuit boards containing failed semiconductors. Board-level investigations often address solder joint integrity, corrosion, and parasitic interactions.

Wafers and Process Monitor Structures

Unpackaged wafers, test keys, and process control monitors used to diagnose inline yield problems such as particle contamination, lithography defects, and parametric outliers before product assembly.

Testing Items

Semiconductor failure analysis experiments typically cover the following test categories, sequenced from least destructive to most destructive so that physical evidence is preserved at every stage:

• Failure verification and electrical characterization: pin-to-pin curve tracing, continuity, leakage, and parametric comparison against known-good units (KGD/KGU).
• Non-destructive inspection: external visual examination, optical microscopy, X-ray radiography (2D/3D CT), and scanning acoustic microscopy (SAM/C-SAM) for internal delamination, voids, and cracks.
• Thermal and photoemission fault isolation: photon emission microscopy (EMMI), lock-in thermography, and magnetic current imaging to localize shorts, leakage paths, and hot spots.
• Electrical fault localization: optical beam induced resistance change (OBIRCH), thermal laser stimulation, laser signal injection microscopy, and e-beam or thermal beam-based techniques.
• Sample preparation: chemical, plasma, laser, or mechanical decapsulation; backside substrate thinning; cross-sectioning; and ion milling.
• Structural and compositional analysis: SEM imaging, energy dispersive X-ray spectroscopy (EDX/EDS), FIB cross-sectioning and circuit edit, transmission electron microscopy (TEM), electron backscatter diffraction (EBSD), and electron probe microanalysis (EPMA).
• Surface and materials analysis: secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), Fourier-transform infrared spectroscopy (FTIR), and atomic force microscopy (AFM).
• Elemental and contamination screening: ion chromatography (IC) for ionic contamination, gas chromatography-mass spectrometry (GC-MS) for organic residues, and total reflection X-ray fluorescence (TXRF) for metallic surface contamination.
• Supplementary environmental stress verification: temperature cycling, high temperature storage, HAST, moisture sensitivity evaluation, and ESD latch-up verification to reproduce the reported failure when necessary.

Testing Methods

Electrical Characterization and Curve Tracing

The experiment begins with failure verification using a curve tracer or semiconductor parameter analyzer to capture I-V curves of every pin relative to ground, power, and neighboring pins. Comparing the failed unit against a known-good device distinguishes opens, shorts, elevated leakage, and abnormal junction behavior, and confirms that the failure is reproducible before destructive steps begin.

X-Ray Inspection and 3D CT Imaging

Transmission X-ray radiography reveals internal features without opening the package, including bond wire integrity, die-attach voids, wire sweep, foreign objects, and cracks. Computed tomography (CT) extends this capability into three dimensions, allowing voxel-level reconstruction of solder joints, through-silicon vias (TSVs), and stacked-die structures.

Scanning Acoustic Microscopy (SAM)

Ultrasonic reflection imaging detects air gaps and interface discontinuities invisible to X-ray, such as mold compound delamination, die attach separation, and interfacial cracks. C-mode SAM is a key screening method aligned with JEDEC and IPC moisture-sensitivity classification practices.

Photon Emission Microscopy (EMMI)

When a biased junction breaks down or a leakage path conducts, excess carriers recombine and emit photons in the near-infrared. An emission microscope images these weak signals through the silicon backside, precisely localizing gate oxide defects, junction spiking, latch-up regions, and saturated transistors.

OBIRCH and Lock-In Thermography

Optical beam induced resistance change scanning detects abnormal resistance paths by locally heating the die surface with a laser and monitoring current change, making it highly effective for locating metallization shorts and via failures. Lock-in thermography, performed from the device backside, senses subtle thermal signatures from low-resistance shorts and leakage sites with micrometer spatial resolution.

Decapsulation and Layer-by-Layer Exposure

After fault localization, the package is opened by chemical etching (fuming acids for epoxy molding compounds), plasma decapsulation, laser ablation, or mechanical milling, chosen to preserve both the die surface and bond wires. Backside analysis requires controlled substrate thinning and local cavity milling using a FIB or mechanical grinder to reach the active circuitry.

FIB Cross-Sectioning and Circuit Edit

A focused gallium or xenon ion beam mills precision cross-sections at the localized defect site, exposing buried layers for SEM inspection. FIB systems also deposit insulating or conductive films to fabricate nanoprobe pads or perform circuit edits that validate root cause hypotheses on prototype silicon.

SEM, EDX, and Elemental Mapping

Scanning electron microscopy provides high-magnification, high-depth-of-field imaging of defects such as melt filaments, cracks, corrosion products, and particles. Energy dispersive X-ray spectroscopy identifies the elemental composition of anomalies, distinguishing contamination, intermetallic formation, corrosion chemistry, and foreign material inclusions.

TEM and Nanoscale Defect Analysis

Lamellae prepared by FIB are examined in a transmission electron microscope to resolve crystallographic defects, gate oxide pinholes, silicide anomalies, dislocations, and interfacial reactions at sub-nanometer scale, supported by EDX and electron energy loss spectroscopy (EELS) for chemical bonding information.

Surface and Contamination Analysis

XPS and AES characterize surface oxidation states and ultrathin films; SIMS profiles dopant distributions and trace impurities with parts-per-billion sensitivity; ion chromatography quantifies ionic residues such as chloride and sulfate that drive electrochemical migration and corrosion-related leakage failures.

Root Cause Synthesis and Reporting

All observations are consolidated into a structured failure analysis report containing failure mode classification, defect location evidence at each analysis stage, physical root cause determination, supporting micrographs and spectra, and categorized corrective action recommendations covering design, materials, process, and application factors.

Applications

Semiconductor failure analysis experiments deliver direct engineering value across the entire electronics product lifecycle:

• Yield improvement: diagnosing wafer-level defects and parametric outliers to drive fab process corrections and ramp yields faster.
• Reliability qualification support: analyzing failures from temperature cycling, HTOL, HAST, ESD, and latch-up stress testing required by AEC-Q100, AEC-Q101, JEDEC, and IEC qualification flows.
• Field failure and warranty analysis: determining whether returned units failed due to electrical overstress, ESD, misuse, or genuine component defects, providing evidence for supplier accountability and design review.
• Assembly and packaging optimization: resolving wire bond non-sticks, delamination, popcorning, solder joint fatigue, and die-attach voiding through SAM, X-ray, and metallographic cross-sectioning.
• Counterfeit component screening: detecting remarked, recycled, or reconditioned parts through package material verification, die architecture inspection, and construction analysis.
• New product introduction (NPI) validation: verifying that first silicon, package developments, and board bring-ups meet electrical and structural expectations before mass production.
• Supply chain quality control: supporting incoming inspection, supplier change notification (PCN) evaluation, and lot acceptance with construction analysis and periodic reliability verification.
• Industry sector coverage: automotive electronics, industrial control, telecommunications, consumer devices, medical electronics, aerospace, and power energy systems all depend on documented failure analysis to meet safety and uptime requirements.

FAQ

What is a semiconductor failure analysis experiment?

It is a systematic laboratory investigation that confirms a device failure, isolates the defect location using electrical, thermal, and optical techniques, and physically examines the anomaly with advanced microscopy to determine the root cause and recommend corrective actions.

Why must non-destructive testing be performed first?

Once a package is opened or the die is sectioned, most electrical and structural evidence is permanently altered. Non-destructive methods such as X-ray, SAM, and visual inspection preserve the failure signature and guide precise, minimal-destructive follow-up steps.

What are the most common semiconductor failure mechanisms?

Frequently identified mechanisms include electrical overstress (EOS), electrostatic discharge (ESD) damage, gate oxide breakdown, metallization open/short defects, electromigration, bond wire lift-off, die attach voiding, mold compound delamination, ionic contamination, corrosion, solder fatigue, and latch-up.

How long does a typical failure analysis take?

Simple electrical verification plus non-destructive screening may be completed in a few working days. Full root cause analysis involving fault isolation, decapsulation, FIB, and TEM examination typically ranges from one to three weeks, depending on failure complexity and sample preparation difficulty.

Which standards govern failure analysis experiments?

Commonly referenced frameworks include JEDEC guidelines (JEP and JESD series), IEC reliability and analysis standards, ASTM material test methods, MIL-STD-883 test methods, IPC assembly and acceptance standards, AEC-Q100 and AEC-Q101 qualification documents, and ISO/IEC 17025 for laboratory competence. Test programs are tailored to the device type, failure symptom, and customer objectives.

What information should be provided when submitting a sample?

Laboratories need the failed units, at least one known-good unit for comparison, a detailed failure description (electrical symptoms, conditions of failure, stress history), circuit context or application notes, package and die information if available, and any constraints on destructive analysis or reporting requirements.

Can failures be analyzed if the device no longer exhibits the fault?

Intermittent or recovered failures can often be investigated through environmental stress reproduction (thermal cycling, vibration, bias stressing) combined with real-time monitoring, followed by fault localization while the anomaly is temporarily active. However, success depends on the reproducibility of the failure condition, and recovered samples carry a higher risk of inconclusive results.